In order to effectively use a dynamic random access memory (RAM) chip a method of addressing the memory locations is required. The RAM contains a set of inputs that comprise the address values. The row and column binary words are combined to form the address which corresponds to a location in memory in which a byte of information may be stored. When an address is input the corresponding location will be susceptible to reading, writing or refreshing. Refresh is a procedure essential to the proper functioning of a dynamic RAM, in which each row address is accessed every few milliseconds to recharge the capacitors that comprise the electrical memory storage units for individual bits in the corresponding row of memory.
The traditional method for carrying out an addressing operation using a finite state machine is to utilize separate counters connected to separate tri-state buffers for each of the functions of read row, read column, write row, write column and refresh. All buffers are separately enabled by a controller and connected to a common address bus to the RAM.
Three significant problems arise from this traditional addressing method. First, the system responds relatively slowly requiring switching between five different buffer systems. Secondly, the system contains a significantly high circuit chip count, adding to size, weight and most importantly, cost of constructing a device containing memory. Finally, the availability of discrete counters and other hardware in larger bit sizes necessary to address a 512 K byte and larger RAM is significantly limited. Without such large capacity hardware, the overall chip count multiplies enormously owing to the need to double the number of chips at each sage of the circuit to accommodate the additional bit capacity.